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 19-3428; Rev 1; 9/05
KIT ATION EVALU ILABLE AVA
Quad Network Power Controller for Power-Over-LAN
Features
IEEE 802.3af Compliant Pin and Function Compatible with LTC4259A Controls Four Independent, -48V-Powered Ethernet Ports in Either Endpoint or Midspan PSE Applications Wide Digital Power Input, VDIG, Common-Mode Range: VEE to (AGND + 7.7V) PD Violation of Class Current Protection PD Detection and Classification Provides Both DC and AC Load Removal Detections I2C-Compatible, 3-Wire Serial Interface Fully Programmable and Configurable Operation Through I2C Interface Current Foldback and Duty-CycleControlled/Programmable Current Limit Short-Circuit Protection with Fast Gate Pulldown Direct Fast Shutdown Control Capability Programmable Direct Interrupt Output Watchdog Mode Enable Hardware Graceful Takeover
General Description
The MAX5945 quad network power controller is designed for use in IEEE 802.3af-compliant power-sourcing equipment (PSE). The device provides power devices (PD) discovery, classification, current-limit, and both DC and AC load disconnect detections. The MAX5945 can be used in either endpoint PSE (LAN switches/routers) or midspan PSE (power injector) applications. The MAX5945 is pin and function compatible with LTC4259A. The MAX5945 can operate autonomously or be controlled by software through an I2C*-compatible interface. Separate input and output data lines (SDAIN and SDAOUT) allow usage with optocouplers. The MAX5945 is a slave device. Its four address inputs allow 16 unique MAX5945 addresses. A separate INT output and four independent shutdown inputs (SHD_) allow fast response from a fault to port shutdown. A RESET input allows hardware reset of the device. A special watchdog feature allows the hardware to gracefully take over control if the software crashes. A cadence timing feature allows the MAX5945 to be used in midspan systems. The MAX5945 is fully software configurable and programmable. A class-overcurrent detection function enables system power management to detect if a PD draws more current than the allowable amount for its class. Other features are input under/overvoltage lockout, overtemperature protection, output-voltage slew-rate limit during startup, power-good, and fault status. The MAX5945's programmability includes gate-charging current, currentlimit threshold, startup timeout, overcurrent timeout, autorestart duty cycle, PD disconnect AC detection threshold, and PD disconnect detection timeout. The MAX5945 is available in a 36-pin SSOP package and is rated for both extended (-40C to +85C) and commercial (0C to +70C) temperature ranges.
MAX5945
Ordering Information
PART MAX5945CAX** MAX5945EAX TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 36 SSOP 36 SSOP
**Future product--contact factory for availability.
Pin Configuration
TOP VIEW
RESET MIDSPAN INT SCL SDAOUT SDAIN 1 2 3 4 5 6 7 8 9 36 OSC_IN 35 AUTO 34 OUT1 33 GATE1 32 SENSE1
Applications
Power-Sourcing Equipment (PSE) Power-Over-LAN/Power-Over-Ethernet Switches/Routers Midspan Power Injectors
*Purchase of I 2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. Typical Operating Circuits appear at end of data sheet.
MAX5945
31 OUT2 30 GATE2 29 SENSE2 28 VEE 27 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND 20 SHD4 19 SHD3
A3 A2 A1
A0 10 DET1 11 DET2 12 DET3 13 DET4 14 DGND 15 VDD 16 SHD1 17 SHD2 18
SSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad Network Power Controller for Power-Over-LAN MAX5945
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VEE, unless otherwise noted.) AGND, DGND, DET_, VDD, RESET, A3, A2, A1, A0, SHD_, OSC_IN, SCL, SDAIN, OUT_ and AUTO............-0.3V to +80V GATE_ (internally clamped, Note 1)....................-0.3V to +11.4V SENSE_ ..................................................................-0.3V to +24V VDD, RESET, A3, A2, A1, A0, SHD_, OSC_IN, SCL, SDAIN and AUTO to DGND ....................................................-0.3V to +7V INT and SDAOUT to DGND....................................-0.3V to +12V Maximum Current into INT, SDAOUT, DET_ .......................80mA Maximum Power Dissipation 36-Pin SSOP (derate 11.4mW/C above +70C) .........941mW Operating Temperature Ranges: MAX5945EAX ..................................................-40C to +85C MAX5945CAX .....................................................0C to +70C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEE may damage the device.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.)
PARAMETER POWER SUPPLIES VAGND Operating Voltage Range VDGND VDD VDD to VDGND, VDGND = VAGND VDD to VDGND, VDGND = VEE OUT_ = VEE, SENSE_ = VEE, DET_ = AGND, all logic inputs open, SCL = SDAIN = VDD, INT and SDAOUT open; measured at AGND in power mode after GATE_ pullup All logic inputs high, measured at VDD Power mode, gate drive on, VGATE = VEE (Note 2) SHD_ = DGND, VGATE_ = VEE + 5V VSENSE = 1V, VGATE_ = VEE + 2V VGATE - VEE , power mode, gate drive on Maximum VSENSE_ allowed during current limit, VOUT_ = VEE (Note 3) Overcurrent VSENSE_ threshold allowed for t tFAULT after startup; VOUT_ = VEE Default, class 0, class 3, class 4 Class 1 Class 2 9 -40 30 VAGND - VEE 32 0 1.71 3.0 60 60 5.50 5.5 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Currents
IEE
4.2
6.8
mA
IDIG GATE DRIVER AND CLAMPING GATE_ Pullup Current Weak GATE_ Pulldown Current Maximum Pulldown Current External Gate Drive CURRENT LIMIT Current-Limit Clamp Voltage VSU_LIM IPU IPDW IPDS VGS
2.7 -50 40 100 10
5.6 -60 50 11 A A mA V
202 178.5 49 90
212
220 196 61 104
mV
Overcurrent Threshold After Startup
VFLT_LIM
mV
Foldback Initial OUT_ Voltage Foldback Final OUT_ Voltage
VFLBK_ST VFLBK_END
VOUT_ - VEE, above which the current-limit trip voltage starts folding back VOUT_ - VEE, above which the current-limit trip voltage reaches VTH_FB
30 50
V V
2
_______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.)
PARAMETER Minimum Foldback CurrentLimit Threshold SENSE_ Input Bias Current SUPPLY MONITORS VEE Undervoltage Lockout VEE Undervoltage-Lockout Hysteresis VEE Overvoltage VEE Overvoltage Hysteresis VEE Undervoltage VDD Overvoltage VDD Undervoltage VDD Undervoltage Lockout VDD Undervoltage-Lockout Hysteresis Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis OUTPUT MONITOR OUT_ Input Current Idle Pullup Current at OUT_ PGOOD High Threshold PGOOD Hysteresis PGOOD Low-to-High Glitch Filter LOAD DISCONNECT DC Load Disconnect Threshold VDCTH Minimum VSENSE allowed before disconnect (DC disconnect active), VOUT_ = VEE 3 4 5 mV IBOUT IDIS PGTH PGHYS tPGOOD Minimum time PGOOD has to be high to set bit in register 10h 2 VOUT = VAGND, all modes OUT_ discharge current, detection and classification off, port shutdown, VOUT_ = VAGND - 2.8V VOUT_ - VEE, OUT_ decreasing 200 1.8 2.0 220 4 2 260 2.2 A A V mV ms VEEUVLO VEEUVLOH VEE_OV VOVH VEE_UV VDD_OV VDD_UV VDDUVLO VDDHYS Ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing (VAGND - VEE) < VEE_UV, VAGND decreasing (VDD - VDGND) > VDD_OV, VDD increasing (VDD - VDGND) < VDD_UV, VDD decreasing Device operates when (VDD - VDGND) > VDDUVLO, VDD increasing 120 39 3.57 2.55 (VAGND - VEE) > VEE_OV, VAGND increasing 61 VAGND - VEE, (VAGND - VEE) increasing 27 28.5 3 62.5 1 40 3.71 2.82 41 3.90 2.97 1.7 64 30 V V V V V V V V mV SYMBOL VTH_FB VOUT_ = VAGND VSENSE_ = VEE CONDITIONS MIN TYP 64 -2 MAX UNITS mV A
MAX5945
TSHD TSHDH
+150 20
C C
_______________________________________________________________________________________
3
Quad Network Power Controller for Power-Over-LAN MAX5945
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.)
PARAMETER AC Load Disconnect Threshold (Note 4) Oscillator Buffer Gain OSC_IN Fail Threshold (Note 5) OSC_IN Input Resistance OSC_IN Input Capacitance Load Disconnect Timer DETECTION Detection Probe Voltage (First Phase) Detection Probe Voltage (Second Phase) Current-Limit Protection Short-Circuit Threshold Open-Circuit Threshold Resistor Detection Window Resistor Rejection Window CLASSIFICATION Classification Probe Voltage Current-Limit Protection VCL IClLIM VAGND - VDET_ during classification VDET_ = VAGND, during classification, measure current through DET_ Class 0, class 1 Classification Current Thresholds ICL Classification current thresholds between classes Class 1, class 2 Class 2, class 3 Class 3, class 4 >Class 4 DIGITAL INPUTS/OUTPUTS (REFERRED to DGND) Digital Input Low Digital Input High VIL VIH 2.4 0.9 V V 16 50 5.5 13.5 21.5 31 45 6.5 14.5 23 33 48 20 75 7.5 15.5 24.5 35 51 mA V mA VDPH1 VDPH2 IDLIM VDCP ID_OPEN RDOK RDBAD VAGND - VDET_ during the first detection phase VAGND - VDET_ during the second detection phase VDET_ = VAGND, during detection, measure current through DET_ If VAGND - VOUT < VDCP after the first detection phase a short circuit to AGND is detected First point measurement current threshold for open condition (Note 7) Detection rejects lower values Detection rejects higher values 30 18.6 3.8 9.0 1.5 4 9.3 1.75 1.62 12.5 26.5 16 4.2 9.6 2.0 V V mA V A k k SYMBOL IACTH AOSC VOSC_FAIL ZOSC COSC_IN tDISC Time from VSENSE < VDCTH or current into DET_ < IACTH to gate shutdown (Note 6) 300 CONDITIONS Current into DET_, ACD_EN_ bit = high, OSC_IN = 2.2V VDET_ / VOSC_IN, ACD_EN_ bit = high, CDET = 400nF Port will not power on if VOSC_IN < VOSC_FAIL and ACD_EN_ bit = high OSC_IN input impedance when all the ACD_EN_ are active MIN 300 2.92 1.8 100 5 400 TYP 325 2.98 1.9 MAX 350 3.04 2.1 UNITS A V/V V k pF ms
4
_______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.)
PARAMETER Internal Input Pullup/Pulldown Resistor Open-Drain Output Low Voltage Open-Drain Leakage TIMING Startup Time tSTART Time during which a current limit set by VSU_LIM is allowed, starts when the GATE_ is turned on (Note 8) Maximum allowed time for an overcurrent condition set by VFLT_LIM after startup (Note 8) Minimum delay between any port turning off, does not apply in the case of a reset Maximum time allowed before detection is completed 2.0 Time allowed for classification Time VAGND must be above the VEEUVLO thresholds before the device operates RSTR bits = 00 Time a port has to wait before turning on after an overcurrent fault, RSTR_EN bit = high RSTR bits = 01 RSTR bits = 10 RSTR bits = 11 Watchdog Clock Period Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time for Start Condition Low Period of the SCL Clock High Period of the SCL Clock tWD fSCL tBUF tHD, STA tLOW tHIGH Rate of decrement of the watchdog timer (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) 1.2 0.6 1.2 0.6 TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6) 400 kHz s s s s 2 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 164 ms ms 50 60 70 ms SYMBOL RDIN VOL IOL CONDITIONS Pullup (pulldown) resistor to VDD (DGND) to set default level ISINK = 15mA Open-drain high impedance, VO = 3.3V MIN 25 TYP 50 MAX 75 0.4 2 UNITS k V A
MAX5945
Fault Time Port Turn-Off Time Detection Time Midspan Mode Detection Delay Classification Time VEEUVLO Turn-On Delay
tFAULT tOFF tDET tDMID tCLASS tDLY
50 0.5
60 0.75
70 1.0 320 2.4 40 4
ms ms ms s ms ms
Restart Timer
tRESTART
_______________________________________________________________________________________
5
Quad Network Power Controller for Power-Over-LAN MAX5945
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.)
PARAMETER Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed SYMBOL tSU, STA tHD, DAT tSU, DAT tR tF tSU, STO CB tSP (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) CONDITIONS MIN 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 150 TYP MAX UNITS s ns ns ns ns s pF ns
Note 2: Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and Description section). Note 3: Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register Map and Description section). Note 4: This is the default value. Threshold can be programmed through serial interface R23h[2:0]. Note 5: AC disconnect works only if VDD - VDGND 3V. Note 6: tDISC can also be programmed through the serial interface (R29h) (see the Register Map and Description section). Note 7: RD = (VOUT_2 - VOUT_1) / (IDET_2 - IDET_1). VOUT_1, VOUT_2, IDET_2 and IDET_1 represent the voltage at OUT_ and the current at DET_ during phase 1 and 2 of the detection. Note 8: Default values. The startup and fault times can also be programmed through the I2C serial interface (see the Register Map and Description section). Note 9: Guaranteed by design. Not subject to production testing.
Typical Operating Characteristics
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, all registers = default setting, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. INPUT VOLTAGE
4.4 4.3 SUPPLY CURRENT (mA) 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 32 37 42 47 52 57 62 INPUT VOLTAGE (V) MEASURED AT AGND
MAX5945 toc01
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5945 toc02
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
MAX5945 toc03
4.5
5.0 4.8 4.6 SUPPLY CURRENT (mA) 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 -40 -15 10 35 60
5.0
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
6
_______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN MAX5945
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, all registers = default setting, TA = +25C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT vs. INPUT VOLTAGE
MAX5945 toc04
VEE UNDERVOLTAGE LOCKOUT vs. TEMPERATURE
MAX5945 toc05
GATE OVERDRIVE vs. INPUT VOLTAGE
9.96 9.94 GATE OVERDRIVE (V) 9.92 9.90 9.88 9.86 9.84 9.82 9.80
MAX5945 toc06
6 MEASURED AT VDD 5 SUPPLY CURRENT (mA) 4 3 2 1 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6
30.0 29.5 29.0 28.5 28.0 27.5 27.0
9.98
UNDERVOLTAGE LOCKOUT (V)
9.78 -40 -15 10 35 60 85 32 37 42 47 52 57 62 TEMPERATURE (C) INPUT VOLTAGE (V)
5.0
INPUT VOLTAGE (V)
GATE OVERDRIVE vs. TEMPERATURE
MAX5945 toc07
SENSE TRIP VOLTAGE vs. TEMPERATURE
MAX5945 toc08
SENSE TRIP VOLTAGE vs. INPUT VOLTAGE
MAX5945 toc09
10.5 10.4 10.3 GATE OVERDRIVE (V) 10.2 10.1 10.0 9.9 9.8 9.7 9.6 9.5 -40 -15 10 35 60
200 195 SENSE TRIP VOLTAGE (mV) 190 185 180 175 170
190
SENSE TRIP VOLTAGE (mV)
188
186
184
182
180 -40 -15 10 35 60 85 32 37 42 47 52 57 62 TEMPERATURE (C) INPUT VOLTAGE (V)
85
TEMPERATURE (C)
FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE
MAX5945 toc10
ZERO-CURRENT DETECTION THRESHOLD vs. TEMPERATURE
MAX5945 toc11
300 250 VSENSE - VEE (mV) 200 150 100 50 0 0 10 20 30 40
5
DETECTION THRESHOLD (mV)
4
3
2
1
50
0 -40
-15
10
35
60
85
VOUT - VEE (V)
TEMPERATURE (C)
_______________________________________________________________________________________
7
Quad Network Power Controller for Power-Over-LAN MAX5945
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, all registers = default setting, TA = +25C, unless otherwise noted.)
OVERCURRENT TIMEOUT (RLOAD = 240 TO 57)
MAX5945 toc12
OVERCURRENT RESPONSE WAVEFORM (RLOAD = 240 TO 57)
MAX5945 toc13
(AGND - OUT) 20V/div 0V IOUT 200mA/div 0A GATE 10V/div VEE INT 2V/div 0V 20ms/div 400s/div IOUT 200mA/div 0A
(AGND - OUT) 20V/div
0V
GATE 10V/div VEE INT 2V/div 0V
SHORT-CIRCUIT RESPONSE TIME
MAX5945 toc14
SHORT-CIRCUIT RESPONSE TIME
MAX5945 toc15
(AGND - OUT) 20V/div
(AGND - OUT) 20V/div
0V IOUT 250mA/div 0A
0V IOUT 5A/div 0A
GATE 10V/div VEE 20ms/div 4s/div
GATE 10V/div VEE
RESET TO OUTPUT TURN-OFF DELAY
MAX5945 toc16
ZERO-CURRENT DETECTION WAVEFORM
MAX5945 toc17
RESET
(AGND - OUT) 20V/div
0V IOUT 200mA/div 0A (AGND - OUT) 20V/div GATE 10V/div VEE 100s/div 100ms/div GATE 10V/div INT 5V/div 0V IOUT 200mA/div
8
_______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN MAX5945
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, all registers = default setting, TA = +25C, unless otherwise noted.)
STARTUP WITH VALID PD (25k AND 0.1F)
MAX5945 toc19
OVERCURRENT RESTART DELAY
MAX5945 toc18
(AGND - OUT) 20V/div 0V
(AGND - OUT) 20V/div 0V IOUT 100mA/div
IOUT 200mA/div 0A GATE 10V/div VEE 400ms/div 100ms/div
GATE_ VEE
DETECTION WITH INVALID PD (25k AND 10F)
MAX5945 toc20
DETECTION WITH INVALID PD (15k)
MAX5945 toc21
(AGND - OUT) 2V/div 0V
(AGND - OUT) 5V/div 0V
IOUT 1mA/div
IOUT 1mA/div 0A
40ms/div
100ms/div
DETECTION WITH INVALID PD (33k)
MAX5945 toc22
STARTUP IN MIDSPAN MODE WITH VALID PD (25k AND 0.1F)
MAX5945 toc23
(AGND - OUT) 20V/div (AGND - OUT) 5V/div 0V 0V IOUT 100mA/div IOUT 1mA/div 0A 0A GATE_ 10V/div VEE 100ms/div 100ms/div
_______________________________________________________________________________________
9
Quad Network Power Controller for Power-Over-LAN MAX5945
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, all registers = default setting, TA = +25C, unless otherwise noted.)
DETECTION WITH MIDSPAN MODE WITH INVALID PD (15k)
MAX5945 toc24
DETECTION WITH MIDSPAN MODE WITH INVALID PD (33k)
MAX5945 toc25
(AGND - OUT) 5V/div 0V
(AGND - OUT) 5V/div 0V
IOUT 1mA/div 0A GATE_ 10V/div VEE 400ms/div 400ms/div
IOUT 1mA/div 0A GATE_ 10V/div VEE
DETECTION WITH OUTPUT SHORTED
MAX5945 toc26
DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 1)
MAX5945 toc27
(AGND - OUT) 5V/div 0V (AGND - OUT) 5V/div 0V
IOUT 1mA/div 0A GATE_ 10V/div VEE 40ms/div 100ms/div
IOUT 1mA/div 0A GATE_ 10V/div VEE
DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 2)
MAX5945 toc28
STARTUP WITH DIFFERENT PD CLASSES
MAX5945 toc29
(AGND - OUT) 5V/div
(AGND - OUT) 5V/div CLASS4
IOUT 2mA/div GATE_ 10V/div 0V 40ms/div
CLASS3 CLASS2 CLASS1 CLASS0 IOUT 10mA/div
100ms/div
10
______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN
Pin Description
PIN 1 NAME RESET FUNCTION Hardware Reset. Pull RESET low for at least 300s to reset the device. All internal registers reset to their default value. The address (A0-A3), and AUTO and MIDSPAN input logic levels latch on during low-to-high transition of RESET. Internally pulled up to VDD with 50k resistor. MIDSPAN Mode Input. An internal 50k pulldown resistor to DGND sets the default mode to endpoint PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section). Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more information about interrupt management). Serial Interface Clock Line Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I2C-compatible system. Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I2C-compatible system. Address Bits. A3, A2, A1, and A0 form the lower part of the device's address. Address inputs default high with an internal 50k pullup resistor to VDD. The address values latch when VDD or VEE ramps up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010. Detection and Classification Voltage Outputs. Use DET1 to set the detection and classification probe voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect scheme (see the Typical Application Circuit). Connect to Digital Ground Positive Digital Supply. Connect to digital supply (referenced to DGND). Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD with a 50k resistor. Analog Ground. Connect to the high-side analog supply.
MAX5945
2
MIDSPAN
3 4 5 6
INT SCL SDAOUT SDAIN
7-10
A3, A2, A1, A0
11-14 15 16 17-20 21 22, 25, 29, 32 23, 26, 30, 33 24, 27, 31, 34 28
DET1, DET2, DET3, DET4 DGND VDD SHD1, SHD2, SHD3, SHD4 AGND
SENSE4, SENSE3, MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and SENSE2, SENSE1 connect a current-sense resistor between SENSE_ and VEE (see the Typical Application Circuit). GATE4, GATE3, GATE2, GATE1 OUT4, OUT3, OUT2, OUT1 VEE Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external FET (see the Typical Application Circuit). MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor (100 to 100k). The low leakage at OUT_ limits the drop across the resistor to less than 100mV (see the Typical Application Circuit). Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1F capacitor between AGND and VEE. AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive low to put the MAX5945 into SHUTDOWN mode. In SHUTDOWN mode, software controls the operational modes of the MAX5945. A 50k internal pulldown resistor defaults AUTO low. AUTO latches when VDD or VEE ramps up and exceeds its UVLO threshold or when the device resets. Software commands can take the MAX5945 out of AUTO while AUTO is high. Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz 10%, 2VP-P 5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below the OSC_FAIL threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
35
AUTO
36
OSC_IN
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11
Quad Network Power Controller for Power-Over-LAN MAX5945
VDD SCL SDAIN SDAOUT SHD_ OSC_IN DGND CURRENT SENSING SERIAL PORT INTERFACE (SPI) A0 DETECTION/ CLASSIFICATION SM PORT STATE MACHINE (SM) ACD_ENABLE 50A A=3 GATE_ AUTO PWR_EN MIDSPAN CENTRAL LOGIC UNIT (CLU) RESET AC DISCONNECT SIGNAL (ACD) 13V CLAMP AC DETECTION 9-BIT ADC CONVERTER 10V A2 REGISTER FILE A3 VOLTAGE SENSING OUT_ OSCILLATOR MONITOR VOLTAGE PROBING AND CURRENT-LIMIT CONTROL DET_
A1
FAST DISCHARGE CONTROL
100mA 90A MAX
INT
ACD REFERENCE CURRENT SENSE_
AGND
ANALOG BIAS/ SUPPLY MONITOR
+10V ANALOG +5V DIG VOLTAGE REFERENCES CURRENT REFERENCES OPEN CIRCUIT (OC)
CURRENT LIMIT (ILIM)
CURRENT-LIMIT DETECTOR
VEE
OVERCURRENT (OVC)
FOLDBACK CONTROL
MAX5945
4mV
182mV
212mV
Figure 1. MAX5945 Functional Diagram
Detailed Description
The MAX5945 four-port network power controller controls -32V to -60V negative supply rail systems. Use the MAX5945, which is compliant with the IEEE 802.3af standard for PSE in power-over-LAN applications. The MAX5945 provides PD discovery, classification, current limit, both DC and AC load disconnect detections, and other necessary functions for an IEEE 802.3af-compli12
ant PSE. The MAX5945 can be used in either endpoint PSE (LAN switch/router) or midspan PSE (power injector) applications. The MAX5945 is fully software-configurable and programmable with more than 25 internal registers. The device features an I2C-compatible, 3-wire serial interface and a class-overcurrent detection. The class-overcurrent detection function enables system power man-
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Quad Network Power Controller for Power-Over-LAN
agement where it detects a PD that draws more current than the allowable amount for its class. The MAX5945's extensive programmability enhances system flexibility and allows for uses in other applications. The MAX5945 has four different operating modes: auto mode, semi-auto mode, manual mode, and shutdown mode (see the Operation Modes section). A special watchdog feature allows the hardware to gracefully take over control if the software/firmware crashes. A cadence timing feature allows the MAX5945 to be used in midspan systems. The MAX5945 provides input undervoltage lockout, input undervoltage detection, input overvoltage lockout, overtemperature protection, output-voltage slew-rate limit during startup, power-good status, and fault status. The MAX5945's programmability includes gate-charging current, current-limit threshold, startup timeout, overcurrent timeout, autorestart duty cycle, PD disconnect AC detection threshold and PD disconnect detection timeout. The MAX5945 communicates with the system microcontroller through an I2C-compatible interface. The MAX5945 features separate input and output data lines (SDAIN and SDAOUT) for use with optocoupler isolation. The MAX5945 is a slave device. Its four address inputs allow 16 unique MAX5945 addresses. A separate INT output and four independent shutdown inputs (SHD_) allow fast interrupt signals between the MAX5945 and the microcontroller. A RESET input allows hardware reset of the device.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off power and clear the events and status registers of the corresponding port. Port reset only resets the events and status registers.
MAX5945
Operation Modes
The MAX5945 contains four independent but identical state machines to provide reliable and real-time control of the four network ports. Each state machine has four different operating modes: auto, semi-auto, manual, and shutdown. Auto mode allows the device to operate automatically without any software supervision. Semiauto mode, upon request, continuously detects and classifies a device connected to a port but does not power up that port until instructed by software. Manual mode allows total software control of the device and is useful in system diagnostic. Shutdown mode terminates all activities and securely turns off power to the ports. Switching between AUTO, SEMI, or MANUAL mode does not take effect until the part finishes its current task. When the port is set into SHUTDOWN mode, all the port operations are immediately stopped and the port remains idle until SHUTDOWN is exited. Automatic (AUTO) Mode Enter automatic (AUTO) mode by forcing the AUTO input high prior to a reset, or by setting R12h[P_ M1,P_M0] to [1,1] during normal operation (see Tables 15 and 15a). In AUTO mode, the MAX5945 performs detection, classification, and powers up the port automatically once a valid PD is detected at the port. If a valid PD is not detected at the port, the MAX5945 repeats the detection routine continuously until a valid PD is detected. Going into AUTO mode, the DET_EN and CLASS_EN bits are set to high and stay high unless changed by software. Using software to set DET_EN and/or CLASS_EN low causes the MAX5945 to skip detection and/or classification. As a protection, disabling the detection routine in AUTO mode will not allow the corresponding port to power up, unless the DET_BYP (R23H[4]) is set to 1. The AUTO status is latched into the register only during a reset. Any changes to the AUTO input after reset is ignored. Semi-Automatic (SEMI) Mode Enter semi-automatic (SEMI) mode by setting R12h[P_M1,P_M0] to [1,0] during normal operation (see Tables 15 and 15a). In SEMI mode, the MAX5945, upon request, performs detection and/or classification repeatedly but does not power up the port(s), regardless of the status of the port connection.
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Reset
Reset is a condition the MAX5945 enters after any of the following conditions: * After power-up (VEE and VDD rise above their UVLO thresholds). * * * Hardware reset. The RESET input is driven low and up high again any time after power-up. Software reset. Writing a 1 into R1Ah[4] any time after power-up. Thermal shutdown.
During a reset, the MAX5945 resets its register map to the reset state as shown in Table 30 and latches in the state of AUTO (pin 35) and MIDSPAN (pin 2). During normal operation, changes at the AUTO and MIDSPAN inputs are ignored. While the condition that caused the reset persists (i.e., high temperature, RESET input low, or UVLO conditions) the MAX5945 will not acknowledge any addressing from the serial interface.
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Quad Network Power Controller for Power-Over-LAN
Setting R19h[PWR_ON_] (Table 21) high immediately terminates detection/classification routines and turns on power to the port(s). R14h[DET_EN_, CLASS_EN_] default to low in SEMI mode. Use software to set R14h[DET_EN_, CLASS_EN_] to high to start the detection and/or classification routines. R14h[DET_EN_, CLASS_EN_] are reset every time the software commands a power-off of the port (either through reset or PWR_OFF). In any other case, the status of the bits is left unchanged (including when the state machine turns off the power because a load disconnect or a fault condition is encountered). MANUAL Mode Enter MANUAL mode by setting R12h[P_M1,P_M0] to [0,1] during normal operation (see Tables 15 and 15a). MANUAL mode allows the software to dictate any sequence of operation. Write a 1 to both R14h[DET_ EN_] and R14h[CLASS_EN_] start detection and classification operations, respectively, and in that priority order. After execution, the command is cleared from the register(s). PWR_ON_ has highest priority. Setting PWR_ON_ high at any time causes the device to immediately enter the powered mode. Setting DET_EN and CLASS_EN high at the same time causes detection to be performed first. Once in the powered state, the device ignores DET_EN_ or CLASS_EN_ commands. When switching to MANUAL mode from another mode, DET_EN_, CLASS_EN_ default to low. These bits become pushbutton rather than configuration bits (i.e., writing ones to these bits while in MANUAL mode commands the device to execute one cycle of detection and/or classification. The bits are reset back to zeros at the end of the execution). Putting the MAX5945 into shutdown mode immediately turns off power and halts all operations to the corresponding port. The event and status bits of the affected port(s) are also cleared. In SHUTDOWN mode, the DET_EN_, CLASS_EN_, and PWR_ON_ commands are ignored. In SHUTDOWN mode, the serial interface operates normally.
MAX5945
PD Detection
When PD detection is activated, the MAX5945 probes the output for a valid PD. After each detection cycle, the device sets the DET_END_ bit R04h/05h[3:0] high and reports the detection results in the status registers R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The DET_END_ bit is reset to low when read through R05h or after a port reset. Both DET_END_ bit status registers are cleared after the port powers down. A valid PD has a 25k discovery signature characteristic as specified in the IEEE 802.3af standard. Table 1 shows the IEEE 802.3af specification for a PSE detecting a valid PD signature (see the Typical Application Circuit and Figure 2). The MAX5945 can probe and categorize different types of devices connected to the port such as a valid PD, an open circuit, a low resistive load, a high resistive load, a high capacitive load, a positive DC supply, or a negative DC supply. During detection, the MAX5945 turns off the external MOSFET and forces two probe voltages through the DET_ input. The current through the DET_ input is measured as well as the voltage at OUT_. A two-point slope measurement is used as specified by the IEEE 802.3af standard to verify the device connected to the port. The MAX5945 implements appropriate settling times and a 100ms digital integration to reject 50Hz/60Hz powerline noise coupling. An external diode, in series with the DET_ input, restricts PD detection to the 1st quadrant as specified by the IEEE 802.3af standard. To prevent damage to non-PD devices and to protect itself from an output short circuit, the MAX5945 limits the current into DET_ to less than 2mA maximum during PD detection. In midspan mode, the MAX5945 waits 2.2s before attempting another detection cycle after every failed detection. The first detection, however, happens immediately after issuing the detection command.
Power Device Classification (PD Classification)
During the PD classification mode, the MAX5945 forces a probe voltage (-18V) at DET_ and measures the current into DET_. The measured current determines the class of the PD. After each classification cycle, the device sets the CL_END_ bit (R04h/05h[7:4]) high and reports the classification results in the status registers R0Ch[6:4], R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit is reset to low when read through register R05h or after a port reset. Both Class_END_ bit status registers are cleared after the port powers down.
Watchdog
R1Dh, R1Eh, and R1Fh registers control watchdog operation. The watchdog function, when enabled, allows the MAX5945 to gracefully take over control or securely shut down the power to the ports in case of software/firmware crashes. Contact the factory for more details.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 1. PSE PI Detection Modes Electrical Requirement (Table 33-2 of the IEEE 802.3af Standard)
PARAMETER Open-Circuit Voltage Short-Circuit Current Valid Test Voltage Voltage Difference Between Test Points Time Between Any Two Test Points Slew Rate Accept Signature Resistance Reject Signature Resistance Open-Circuit Resistance Accept Signature Capacitance Reject Signature Capacitance Signature Offset Voltage Tolerance Signature Offset Current Tolerance SYMBOL VOC ISC VVALID VTEST tBP VSLEW RGOOD RBAD ROPEN CGOOD CBAD VOS IOS MIN -- -- 2.8 1 2 -- 19 < 15 500 -- 10 0 0 MAX 30 5 10 -- -- 0.1 26.5 > 33 -- 150 -- 2.0 12 UNITS V mA V V ms V/s k k k nF F V A This timing implies a 500Hz maximum probing frequency ADDITIONAL INFORMATION In detection mode only In detection mode only
Table 2. PSE Classification of a PD (Table 33-4 of the IEEE 802.3af Standard)
MEASURED ICLASS (mA) 0 to 5 > 5 and < 8 8 to 13 > 13 and < 16 16 to 21 > 21 and < 25 25 to 31 > 31 and <35 35 to 45 > 45 and < 51 CLASSIFICATION Class 0 May be Class 0 and 1 Class 1 May be Class 0, 1, or 2 Class 2 May be Class 0, 2, or 3 Class 3 May be Class 0, 3, or 4 Class 4 May be Class 0 or 4
Table 2 shows the IEEE 802.3af requirement for a PSE classifying a PD at the power interface (PI).
Powered State
When the part enters PWR MODE, the tSTART and tDISC timers are reset. Before turning on the power, the part
checks if any other port is not turning on and if the tFAULT timer is zero. Another check is performed if the ACD_EN bit is set, in this case OSC_FAIL bit must be low (oscillator is okay) for the port to be powered. If these conditions are met then the part enters startup where it turns on power to the port. An internal signal, POK_, is asserted high when VOUT is within 2V from VEE. PGOOD_ status bits are set high if POK_ stays high longer than tPGOOD. PGOOD immediately resets when POK goes low. The PWR_CHG bit sets when a port powers up or down. PWR_EN sets when a port powers up and resets when a port shuts down. The port shutdown timer lasts 0.5ms and prevents other ports from turning off during that period, except in the case of emergency shutdowns (RESET = L, RESET_IC = H, VEEUVLO, VDDUVLO, and TSHD). The MAX5945 always checks the status of all ports before turning off. A priority logic system determines the order to prevent the simultaneous turn-on or turn-off of the ports. The port with the lesser ordinal number gets priority over the others (i.e., port 1 turns on first, port 2 second, port 3 third and port 4 fourth). Setting PWR_OFF_ high turns off power to the corresponding port.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Overcurrent Protection
80ms 0V 150ms tDETI 150ms tDETII 21.3ms tCLASS t
0V
-4V
-9V
OUT_
-18V
-48V
Figure 2. Detection, Classification, and Power-Up Port Sequence
POK
tPGOOD
A sense resistor (RS), connected between SENSE_ and V EE , monitors the load current. Under all circumstances, the voltage across R S never exceeds the threshold V SU_LIM. If SENSE_ exceeds V SU_LIM, an internal current-limiting circuit regulates the GATE voltage, limiting the current to ILIM = VSU_LIM / RS. During transient conditions, if the SENSE_ voltage exceeds VSU_LIM, a fast pulldown circuit activates to quickly recover from the current overshoot. During startup, if the current-limit condition persists, when the startup timer, t START , times out, the port shuts off and the STRT_FLT_ bit is set. In normal powered state, the MAX5945 checks for overcurrent conditions as determined by VFLT_LIM = ~88% of VSU_LIM. The tFAULT counter sets the maximum allowed continuous overcurrent period. The tFAULT counter increases when VSENSE exceeds VFLT_LIM and decreases at a slower pace when VSENSE drops below VFLT_LIM. A slower decrement for the tFAULT counter allows for detecting repeated short-duration overcurrents. When the counter reaches the tFAULT limit, the MAX5945 powers off the port and asserts the IMAX_FLT_ bit. For a continuous overstress, a fault latches exactly after a period of tFAULT. VSU_LIM, is programmable using R27h[4-7]. tFAULT is programmable using R16h[2-3] and R28[4-7]. After power-off due to an overcurrent fault, and if the RSTR_EN bit is set, the tFAULT timer is not immediately reset but starts decrementing at the same slower pace. The MAX5945 allows the port to be powered on only when the tFAULT counter is at zero. This feature sets an automatic duty-cycle protection to the external MOSFET to avoid overheating. The duty cycle is programmable using R16h[6-7]. The MAX5945 continuously flags when the current exceeds the maximum current allowed for the class as indicated in the CLASS status register. When class overcurrent occurs, the MAX5945 sets the IVC bit in register R09h.
Foldback Current
PGOOD
During startup and normal operation, an internal circuit senses the voltage at OUT_ and reduces the currentlimit value when (VOUT_ - VEE) > 30V. The foldback function helps to reduce the power dissipation on the FET. The current limit eventually reduces to 1/3 of ILIM when (VOUT_ - VEE ) > 50V (see Figure 4).
Figure 3. PGOOD Timing
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Quad Network Power Controller for Power-Over-LAN
(VSENSE_ - VEE) VSU_LIM
VSU_LIM / 3
30V
50V
(VOUT_ - VEE)
Figure 4. Foldback Current Characteristics
digital supply for compatibility with the internal logic. The MAX5945 also features a VDD undervoltage lockout (VDDUVLO) of +1.35V. A VDDUVLO condition keeps the MAX5945 in reset and the ports shut off. Bit 0 in the supply event register shows the status of V DDUVLO (Table 11) after VDD has recovered. All logic inputs and outputs reference to DGND. DGND and AGND are completely isolated internally to the MAX5945. In a completely isolated system, the digital signal can be referenced indifferently to VAGND or VEE or at voltages even higher than AGND (up to 60V). VDD - VDGND must be greater than 3.0V when VDGND (VEE + 3.0V) When using the AC disconnect detection feature, AGND must be connected directly to DGND and VDD must be greater than +3V. In this configuration, connect DGND to AGND at a single point in the system as close to MAX5945 as possible.
MAX5945
MOSFET Gate Driver
Connect the gate of the external n-channel MOSFET to GATE_. An internal 50A current source pulls GATE_ to (VEE + 10V) to turn on the MOSFET. An internal 40A current source pulls down GATE_ to VEE to turn off the MOSFET. The pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. The pullup current (gate-charging current) is programmable using R23h[5-7]. Use the following equation to set the maximum slew rate: VOUT I = GATE t CGD where CGD is the total capacitance between GATE and DRAIN of the external FET. Current limit and the capacitive load at the drain control the slew rate during startup. During current-limit regulation, the MAX5945 manipulates the GATE_ voltage to control the voltage at SENSE_. A fast pulldown activates if SENSE_ overshoots the limit threshold. The fast pulldown current increases with the amount of overshoot. The maximum fast pulldown current is 100mA. During turn-off, when the GATE voltage reaches a value lower than 1.2V, a strong pulldown switch is activated to keep the FET securely off.
Hardware Shutdown
SHD_ shuts down the respective ports without using the serial interface. Hardware shutdown offers an emergency turn-off feature that allows a fast disconnect of the power supply from the port. Pull SHD_ low to remove power.
Interrupt
The MAX5945 contains an open-drain logic output (INT) that goes low when an interrupt condition exists. R00h and R01h (Tables 5 and 6) contain the definitions of the interrupt registers. The mask register R01h determines events that trigger an interrupt. As a response to an interrupt, the controller reads the status of the event register to determine the cause of the interrupt and takes subsequent actions. Each interrupt event register also contains a clear-on-read (CoR) register. Reading through the CoR register address clears the interrupt. INT remains low when reading the interrupt through the read-only addresses. For example, to clear a startup fault on port 4 read address 09h (see Table 10). Use the global pushbutton bit on register 1Ah (bit 7, Table 22) to clear interrupts, or use a software or hardware reset.
Undervoltage and Overvoltage Protection
The MAX5945 contains several undervoltage and overvoltage protection features. Table 11 in the Register Map and Description section shows a detailed list of the undervoltage and overvoltage protection features. An internal V EE undervoltage lockout (V EEUVLO) circuit keeps the MOSFET off and the MAX5945 in reset until VAGND - VEE exceeds 29V for more than 3ms. An internal VEE overvoltage (VEE_OV) circuit shuts down the ports when (VAGND - VEE) exceeds 60V. The digital supply also contains an undervoltage lockout (VDDUVLO).
Digital Logic
VDD supplies power for the internal logic circuitry. VDD ranges from +1.71V to +3.7V and determines the logic thresholds for the CMOS connections (SDAIN, SDAOUT, SCL, AUTO, SHD_, A_). This voltage range enables the MAX5945 to interface with a nonisolated low-voltage microcontroller. The MAX5945 checks the
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Quad Network Power Controller for Power-Over-LAN MAX5945
The MAX5945 also features three other undervoltage and overvoltage interrupts: VEE undervoltage interrupt (VEEUV), VDD undervoltage interrupt (VDDUV), and VDD overvoltage interrupt (VDDOV). A fault latches into the supply events register (Table 11) but the MAX5945 does not shut down the ports with a VEEUV, VDDUV, or VDDOV.
Table 3. MAX5945 Address
0 1 0 A3 A2 A1 A0 R/W
Thermal Shutdown
If the MAX5945 die temperature reaches +150C, an overtemperature fault generates and the MAX5945 shuts down and the MOSFETs turn off. The die temperature of the MAX5945 must cool down below +130C to remove the overtemperature fault condition. After a thermal shutdown, the part is reset.
DC Disconnect Monitoring
Setting R13h[DCD_EN_] bits high enable DC load monitoring during a normal powered state. If SENSE_ falls below the DC load disconnect threshold, VDCTH, for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port. tDISC is programmable using R16h[0-1] and R27h[0-3].
Address Inputs
A3, A2, A1, and A0 represent the four LSBs of the chip address, the complete 7-bit chip address (see Table 3). The four LSBs latch on the low-to-high transition of RESET or after a power-supply start (either on VDD or VEE). Address inputs default high through an internal 50k pullup resistor to V DD . The MAX5945 also responds to the call through a global address 60h (see the Global Addressing and Alert Response Protocol section).
AC Disconnect Monitoring
The MAX5945 features AC load disconnect monitoring. Connect an external sine wave to OSC_IN. The oscillator requirements are: * Frequency x VP-P = 200VP-P x Hz 15% * * * Positive peak voltage > +2V Frequency > 60Hz A 100Hz 10%, 2V P-P 5%, with +1.2V offset (VPEAK = +2.2V, typ) is recommended.
I2C-Compatible Serial Interface
The MAX5945 operates as a slave that sends and receives data through an I2C-compatible, 2-wire or 3wire interface. The interface uses a serial data input line (SDAIN), a serial data output line (SDAOUT), and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX5945, and generates the SCL clock that synchronizes the data transfer. In most applications, connect the SDAIN and the SDAOUT lines together to form the serial data line (SDA). Using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. The MAX5945 SDAIN line operates as an input. The MAX5945 SDAOUT operates as an open-drain output. A pullup resistor, typically 4.7k, is required on SDAOUT. The MAX5945 SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters, or if the master in a single-master system has an open-drain SCL output. Serial Addressing Each transmission consists of a START condition (Figure 7) sent by a master, followed by the MAX5945 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition.
The MAX5945 buffers and amplifies 3x the external oscillator signal and sends the signal to DET_, where the sine wave is AC coupled to the output. The MAX5945 senses the presence of the load by monitoring the amplitude of the AC current returned to DET_ (see the Functional Diagram). Setting R13h[ACD_EN_] bits high enable AC load disconnect monitoring during the normal powered state. If the AC current peak at the DET_ pin falls below IACTH for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port. IACTH is programmable using R23h[0-3]. An internal comparator checks for a proper amplitude of the oscillator input. If the positive peak of the input sinusoid falls below a safety value of 2V, OSC_FAIL sets and the port shuts down. Power cannot be applied to the ports when ACD_EN is set high and OSC_FAIL is set high. Leave OSC_IN unconnected or connect it to DGND when not using AC disconnect detection. When using the AC disconnect detection feature, connect AGND directly to DNGD as close as possible to the IC. The MAX5945 also requires a VDD of greater than +3V for this function. See the Typical Application Circuit with AC disconnect for other external component requirements.
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Quad Network Power Controller for Power-Over-LAN MAX5945
SDAIN tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO
SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 5. 2-Wire Serial Interface Timing Details
SDAIN/SDA tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO
SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 6. 3-Wire Serial Interface Timing Details
SDA/ SDAIN SCL
SDA
SCL
S START
P STOP
. DATA LINE STABLE; CHANGE OF DATA VALID DATA ALLOWED
Figure 7. Start and Stop Conditions
Figure 8. Bit Transfer
Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The stop condition frees the bus for another transmission.
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Quad Network Power Controller for Power-Over-LAN MAX5945
START CONDITION 1 2 CLOCK PULSE FOR ACKNOWLEDGEMENT
SCL
8
9
SDA BY TRANSMITTER S SDA BY RECEIVER
Figure 9. Acknowledge
MSB SDA 0 1 0 A3 A2 A1
LSB A0 R/W ACK
SCL
Figure 10. Slave Address
Bit Transfer Each clock pulse transfers one data bit (Figure 8). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 9), which the recipient uses as a handshake receipt of each byte of data. Thus each byte effectively transferred requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA (or the SDAOUT in the 3-wire interface) during the acknowledge clock pulse, so the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5945, the MAX5945 generates the acknowledge bit. When the MAX5945 transmits to the master, the master generates the acknowledge bit. Slave Address The MAX5945 has a 7-bit long slave address (Figure 10). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for a read command. 010 always represent the first three bits (MSBs) of the MAX5945 slave address. Slave address bits A3, A2, A1, and A0 represent the states of the MAX5945's A3, A2, A1, and A0 inputs, allowing up to sixteen MAX5945 devices to share the bus. The states of the A3, A2, A1,
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and A0 latch in upon the reset of the MAX5945 into register R11h. The MAX5945 monitors the bus continuously, waiting for a START condition followed by the MAX5945's slave address. When the MAX5945 recognizes its slave address, it acknowledges and is then ready for continued communication. Global Addressing and Alert Response Protocol The global address call is used in writing mode to write the same register to multiple devices (address 0x60). In read mode (address 0x61), the global address call is used as the alert response address. When responding to a global call, the MAX5945 puts out on the data line its own address whenever its interrupt is active and so does every other device connected to the SDAOUT line that has an active interrupt. After every bit is transmitted, the MAX5945 checks that the data line effectively corresponds to the data it is delivering. If it is not, it then backs off and frees the data line. This litigation protocol always allows the part with the lowest address to complete the transmission. The microcontroller can then respond to the interrupt and take proper actions. The MAX5945 does not reset its own interrupt at the end of the alert response protocol. The microcontroller has to do it by clearing the event register through their CoR addresses or activating the CLR_INT pushbutton.
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Quad Network Power Controller for Power-Over-LAN MAX5945
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX5945 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8
CONTROL BYTE ACKNOWLEDGE FROM MAX5945
A
P
Figure 11. Control Byte Received
ACKNOWLEDGE FROM MAX5945 HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM MAX5945 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
ACKNOWLEDGE FROM MAX5945 D5 D4 D3 D2 D1 D0
CONTROL BYTE
A
DATA BYTE 1 BYTE
A
P
AUTO-INCREMENT MEMORY WORD ADDRESS
Figure 12. Control and Single Data Byte Received
ACKNOWLEDGE FROM MAX5945 HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM MAX5945 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
ACKNOWLEDGE FROM MAX5945 D5 D4 D3 D2 D1 D0
CONTROL BYTE
A
DATA BYTE n BYTES
A
P
AUTO-INCREMENT MEMORY WORD ADDRESS
Figure 13. `n' Data Bytes Received
Message Format for Writing the MAX5945 A write to the MAX5945 comprises of the MAX5945's slave address transmission with the R/W bit set to 0, followed by at least one byte of information. The first byte of information is the command byte (Figure 11). The command byte determines which register of the MAX5945 is written to by the next byte, if received. If the MAX5945 detects a STOP condition after receiving the command byte, then the MAX5945 takes no further action beyond storing the command byte. Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the
MAX5945 selected by the command byte. If the MAX5945 transmits multiple data bytes before the MAX5945 detects a STOP condition, these bytes store in subsequent MAX5945 internal registers because the control byte address auto-increments. Any bytes received after the control byte are data bytes. The first data byte goes into the internal register of the MAX5945 selected by the control byte (Figure 8). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are stored in subsequent MAX5945 internal registers because the control byte address auto-increments.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 4. Auto-Increment Rules
COMMAND BYTE ADDRESS RANGE 0x00 to 0x26 0x26 AUTO-INCREMENT BEHAVIOR Command address will autoincrement after byte read or written Command address remains at 0x26 after byte written or read
Register Map And Description
The interrupt register (Table 5) summarizes the event register status and is used to send an interrupt signal (INT goes low) to the controller. Writing a 1 to R1Ah[7] clears all interrupt and events registers. A reset sets R00h to 00h. INT_EN (R17h[7]) is a global interrupt mask (Table 6). The MASK_ bits activate the corresponding interrupt bits in register R00h. Writing a 0 to INT_EN (R17h[7]) disables the INT output. A reset sets R01h to AAA00A00b, where A is the state of the AUTO input prior to the reset. The power event register (Table 7) records changes in the power status of the four ports. Any change in PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1. PG_CHG_ and PWEN_CHG_ trigger on the edges of PGOOD_ and PWR_EN_ and do not depend on the actual level of the bits. The power event register has two addresses. When read through the R02h address, the content of the register is left unchanged. When read through the CoR R03h address, the register content will be cleared. A reset sets R02h/R03h = 00h. DET_END_/CL_END_ is set high whenever detection/ classification is completed on the corresponding port. A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1 in any of the DET_END_ bits forces R00h[3] to 1. As with any other events register, the detect event register (Table 8) has two addresses. When read through the R04h address, the content of the register is left unchanged. When read through the CoR R05h address, the register content will be cleared. A reset sets R04h/R05h = 00h. LD_DISC_ is set high whenever the corresponding port shuts down due to detection of load removal. IMAX_FLT_ is set high when the port shuts down due to an extended overcurrent event after a successful startup. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1. A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1. As with any of the other events register, the fault event register (Table 9) has two addresses. When read through the R06h address, the content of the register is left unchanged. When read through the CoR R07h address, the register content will be cleared. A reset sets R06h/R07h = 00h.
Message Format for Reading The MAX5945 reads using the MAX5945's internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. The pointer auto-increments after reading each data byte using the same rules as for a write. Thus, a read is initiated by first configuring the MAX5945's command byte by performing a write (Figure 12). The master now reads `n' consecutive bytes from the MAX5945, with the first data byte read from the register addressed by the initialized command byte (Figure 13). When performing read-after-write verification, remember to reset the command byte's address because the stored control byte address autoincrements after the write. Operation with Multiple Masters When the MAX5945 operates on a 2-wire interface with multiple masters, a master reading the MAX5945 should use repeated starts between the write that sets the MAX5945's address pointer, and the read(s) that takes the data from the location(s). It is possible for master 2 to take over the bus after master 1 has set up the MAX5945's address pointer but before master 1 has read the data. If master 2 subsequently resets the MAX5945's address pointer then master 1's read may be from an unexpected location. Command Address Auto-Incrementing Address auto-incrementing allows the MAX5945 to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX5945 generally increments after each data byte is written or read (Table 4). The MAX5945 is designed to prevent overwrites on unavailable register addresses and unintentional wrap-around of addresses.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 5. Interrupt Register
ADDRESS = 00h SYMBOL SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R DESCRIPTION Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh (Table 8). Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h (Table 7). Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register R06h/R07h (Table 6). Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register R04h/R05h (Table 5) Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register R04h/R05h (Table 5). Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h (Table 6). Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h (Table 4). Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register R02h/R03h (Table 4).
Table 6. Interrupt Mask Register
ADDRESS = 01h SYMBOL MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Interrupt mask bit 7. A logic high enables the SUP_FLT interrupts. A logic low disables the SUP_FLT interrupts. Interrupt mask bit 6. A logic high enables the TSTR_FLT interrupts. A low disables the TSTR_FLT interrupts. Interrupt mask bit 5. A logic high enables the IMAX_FLT interrupts. A logic low disables the IMAX_FLT interrupts. Interrupt mask bit 4. A logic high enables the CL_END interrupts. A logic low disables the CL_END interrupts. Interrupt mask bit 3. A logic high enables the DET_END interrupts. A logic low disables the DET_END interrupts. Interrupt mask bit 2. A logic high enables the LD_DISC interrupts. A logic low disables the LD_DISC interrupts. Interrupt mask bit 1. A logic high enables the PG_INT interrupts. A logic low disables the PG_INT interrupts. Interrupt mask bit 0. A logic high enables the PEN_INT interrupts. A logic low disables the PEN_INT interrupts.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 7. Power Event Register
ADDRESS = SYMBOL PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1 PWEN_CHG4 PWEN_CHG3 PWEN_CHG2 PWEN_CHG1 BIT 7 6 5 4 3 2 1 0 02h R/W R R R R R R R R 03h R/W CoR CoR CoR CoR CoR CoR CoR CoR PGOOD change event for port 4 PGOOD change event for port 3 PGOOD change event for port 2 PGOOD change event for port 1 Power enable change event for port 4 Power enable change event for port 3 Power enable change event for port 2 Power enable change event for port 1 DESCRIPTION
Table 8. Detect Event Register
ADDRESS = SYMBOL CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1 BIT 7 6 5 4 3 2 1 0 04h R/W R R R R R R R R 05h R/W CoR CoR CoR CoR CoR CoR CoR CoR Classification completed on port 4 Classification completed on port 3 Classification completed on port 2 Classification completed on port 1 Detection completed on port 4 Detection completed on port 3 Detection completed on port 2 Detection completed on port 1 DESCRIPTION
Table 9. Fault Event Register
ADDRESS = SYMBOL LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1 BIT 7 6 5 4 3 2 1 0 06h R/W R R R R R R R R 07h R/W CoR CoR CoR CoR CoR CoR CoR CoR Disconnect on port 4 Disconnect on port 3 Disconnect on port 2 Disconnect on port 1 Overcurrent on port 4 Overcurrent on port 3 Overcurrent on port 2 Overcurrent on port 1 DESCRIPTION
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 10. Startup Event Register
ADDRESS = SYMBOL IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1 BIT 7 6 5 4 3 2 1 0 08h R/W R R R R R R R R 09h R/W CoR CoR CoR CoR CoR CoR CoR CoR Class overcurrent flag for port 4 Class overcurrent flag for port 3 Class overcurrent flag for port 2 Class overcurrent flag for port 1 Startup failed on port 4 Startup failed on port 3 Startup failed on port 2 Startup failed on port 1 DESCRIPTION
Table 11. Supply Event Register
ADDRESS = SYMBOL TSD VDD_OV VDD_UV VEE_UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO BIT 7 6 5 4 3 2 1 0 0Ah R/W R R R R R R R R 0Bh R/W CoR CoR CoR CoR CoR CoR CoR CoR Overtemperature shutdown VDD overvoltage condition VDD undervoltage condition VEE undervoltage lockout condition VEE overvoltage condition VEE undervoltage condition Oscillator amplitude is below limit VDD undervoltage lockout condition DESCRIPTION
Table 12. Port Status Registers
ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh SYMBOL Reserved CLASS_ Reserved DET_ST_ BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R DESCRIPTION Reserved CLASS_[2] CLASS_[1] CLASS_[0] Reserved DET_[2] DET_[1] DET_[0]
If the port remains in current limit or the PGOOD condition is not met at the end of the startup period, the port shuts down and the corresponding STRT_FLT_ is set to 1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1. IVC_ is set to 1 whenever the port current exceeds the
maximum allowed limit for the class (determined during the classification process). A 1 in any of IVC_ forces R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1, the port will also limit the load current according to its class as specified in the Electrical Characteristics table. As with any other events register, the startup event register (Table 10) has two addresses. When read through the R08h address, the content of the register is left unchanged. When read through the CoR R09h address, the register content will be cleared. A reset sets R08h/R09h = 00h. The MAX5945 continuously monitors the power supplies and sets the appropriate bits in the supply event register (Table 11). VDD_OV / VEE_OV is set to 1 whenever VDD / VEE exceeds its overvoltage threshold. VDD_UV / VEE_UV is set to 1 whenever VDD / VEE falls below its undervoltage threshold. OSC_FAIL is set to 1 whenever the amplitude of the oscillator signal at the OSC_input falls below a level that might compromise the AC disconnect detection
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 12a. Detection Result Decoding Chart
DET_ST_[2:0] 000 001 010 011 100 101 110 111 DETECTED None DCP HIGH CAP RLOW DET_OK RHIGH OPEN0 DCN Detection status unknown Positive DC supply connected at the port (AGND - VOUT_ < 1.65V) High capacitance at the port (>5F) Low resistance at the port. RPD < 17k. Detection pass. 17k > RPD > 28k. High resistance at the port. RPD > 28k. Open port (I < 12.5A) Negative DC supply connected to the port (VOUT - VEE < 2V) DESCRIPTION
Table 12b. Classification Result Decoding Chart
CLASS_[2:0] 000 001 010 011 100 101 110 111 Unknown 1 2 3 4 Undefined (treated as CLASS 0) 0 Current limit (>ICILIM) CLASS RESULT
sets R0Ah/R0Bh to 00100001 if VDD comes up after VEE or to 00010100 if VEE comes up after VDD. The port status register (Table 12) records the results of the detection and classification at the end of each phase in three encoding bits each. R0Ch contains detection and classification status of port 1. R0Dh corresponds to port 2, R0Eh corresponds to port 3 and R0Fh corresponds to port 4. Tables 12a and 12b show the detection/classification result decoding charts, respectively. As a protection, when POFF_CL (R17h[3], Table 20) is set to 1, the MAX5945 prohibits turning on power to the port that returns a status 111 after classification. A reset sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h. PGOOD_ is set to 1 (Table 13) at the end of the power-up startup period if the power-good condition is met (0 < (VOUT - VEE) < PGTH). The power-good condition must remain valid for more than tPGOOD to assert PGOOD_. PGOOD_ is reset to 0 whenever the output falls out of the power-good condition. A fault condition immediately forces PGOOD_ low. PWR_EN_ is set to 1 when the port power is turned on. PWR_EN_ resets to 0 as soon as the port turns off. Any transition of PGOOD_ and PWR_EN_ bits set the corresponding bit in the power event registers R02h/R03h (Table 7). A reset sets R10h = 00h. A3, A2, A1, A0 (Table 14) represent the four LSBs of the MAX5945 address (Table 3). During a reset, the device latches into R11h. These four bits address from the corresponding inputs as well as the state of the MIDSPAN and AUTO inputs. Changes to those inputs during normal operation are ignored. The MAX5945 uses two bits for each port to set the mode of operation (Table 15). Set the modes according to Table 15a. A reset sets R12h = AAAAAAAA where A represents the latched-in state of the AUTO input prior to the reset. Use software to change the mode of operation.
function. OSC_FAIL generates an interrupt only if at least one of the ACD_EN (R13h[7:4]) bits is set high. A thermal-shutdown circuit monitors the temperature of the die and resets the MAX5945 if the temperature exceeds +150C. TSD is set to 1 after the MAX5945 returns to normal operation. TSD is also set to 1 after every UVLO reset. When VDD and/or |VEE| is below its undervoltage lockout (UVLO) threshold, the MAX5945 is in reset mode and securely holds all ports off. When VDD and |VEE| rise to above their respective UVLO thresholds, the device comes out of reset as soon as the last supply crosses the UVLO threshold. The last supply corresponding UV and UVLO bits in the supply event register will be set to 1. A 1 in any supply event register's bits forces R00h[7] to 1. As with any other events register, the supply event register has two addresses. When read through the R0Ah address, the content of the register is left unchanged. When read through the CoR R0Bh address, the register content will be cleared. A reset
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 13. Power Status Register
ADDRESS = 10h SYMBOL PGOOD4 PGOOD3 PGOOD2 PGOOD1 PWR_EN4 PWR_EN3 PWR_EN2 PWR_EN1 BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Power-good condition on port 4 Power-good condition on port 3 Power-good condition on port 2 Power-good condition on port 1 Power is enabled on port 4 Power is enabled on port 3 Power is enabled on port 2 Power is enabled on port 1 DESCRIPTION
Table 14. Address Input Status Register
ADDRESS = 11h SYMBOL Reserved Reserved A3 A2 A1 A0 MIDSPAN AUTO BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Reserved Reserved Device address, A3 pin latched-in status Device address, A2 pin latched-in status Device address, A1 pin latched-in status Device address, A0 pin latched-in status MIDSPAN input's latched-in status AUTO input's latched-in status DESCRIPTION
Table 15. Mode Register
ADDRESS = 12h SYMBOL P4_M1 P4_M0 P3_M1 P3_M0 P2_M1 P2_M0 P1_M1 P1_M0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W M0DE[1] for port 4 M0DE[0] for port 4 M0DE[1] for port 3 M0DE[0] for port 3 M0DE[1] for port 2 M0DE[0] for port 2 M0DE[1] for port 1 M0DE[0] for port 1 DESCRIPTION
Software resets of ports (RESET_P_ bit, Table 22) do not affect the mode register. Setting DCD_EN_ to 1 enables the DC load disconnect detection feature (Table 16). Setting ACD_EN_ to 1 enables the AC load disconnect feature. If enabled, the load disconnect detection starts during power mode and after startup when the corresponding PGOOD_ bit in register R10h (Table 13) goes high. A Reset sets
R13h = 0000AAAA where A represents the latched-in state of the AUTO input prior to the reset. Setting DET_EN_/CLASS_EN_ to 1 (Table 17) enables load detection/classification, respectively. Detection always has priority over classification. To perform classification without detection, set the DET_EN_ bit low and CLASS_EN_ bit high.
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Quad Network Power Controller for Power-Over-LAN
In MANUAL mode, R14h works like a pushbutton. Set the bits high to begin the corresponding routine. The bit clears after the routine finishes. When entering AUTO mode, R14h defaults to FFh. When entering MANUAL mode, R14h defaults to 00h. When entering SEMI mode, R1h is left unchanged but it is reset every time the software commands power off the port. A reset or power-up sets R14h = AAAAAAAAb where A represents the latched-in state of the AUTO input prior to the reset. Setting BCKOFF_ to 1 (Table 18) enables Cadence timing on each port where the port backs off and waits 2.2s after each failed load discovery detection. The IEEE
MAX5945
802.3af standard requires a PSE that delivers power through the spare pairs (midspan PSE) to have cadence timing. A reset sets R14h = 0000XXXX where X is the logic AND of the MIDSPAN and AUTO input state prior to a reset. BCKOFF_ can be changed by software at any time while changes to the MIDSPAN and AUTO input state during normal operation are ignored. TSTART[1,0] (Table 19) programs the startup timers, startup time is the time the port is allowed to be in current limit during startup. TFAULT_[1,0] programs the fault time. Fault time is the time allowable for the port to be in current limit during normal operation. RSTR[1,0] programs the discharge rate of the TFAULT_ counter and effectively sets the time the port remains off after an overcurrent fault. TDISC[1,0] programs the load disconnect detection time. The device turns off power to the port if it fails to provide a minimum power maintenance signal for longer than the load disconnect detection time (TDISC). Set the bits in R16h to scale the TSTART, TFAULT, and TDISC to a multiple of their nominal value specified in the Electrical Characteristics table. R27h and R28h fur-
Table 15a. Mode Status
MODE 00 01 10 11 DESCRIPTION Shutdown MANUAL Semi AUTO AUTO
Table 16. Load Disconnect Detection Enable Register
ADDRESS = 13h SYMBOL ACD_EN4 ACD_EN3 ACD_EN2 ACD_EN1 DCD_EN4 DCD_EN3 DCD_EN2 DCD_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Enable AC disconnect detection on port 4 Enable AC disconnect detection on port 3 Enable AC disconnect detection on port 2 Enable AC disconnect detection on port 1 Enable DC disconnect detection on port 4 Enable DC disconnect detection on port 3 Enable DC disconnect detection on port 2 Enable DC disconnect detection on port 1
Table 17. Detection and Classification Enable Register
ADDRESS = 14h SYMBOL CLASS_EN4 CLASS_EN3 CLASS_EN4 CLASS_EN3 DET_EN4 DET_EN3 DET_EN2 DET_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable classification on port 4 Enable classification on port 3 Enable classification on port 2 Enable classification on port 1 Enable detection on port 4 Enable detection on port 3 Enable detection on port 2 Enable detection on port 1 DESCRIPTION
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 18. Backoff Enable Register
ADDRESS = 15h SYMBOL Reserved Reserved Reserved Reserved BCKOFF4 BCKOFF3 BCKOFF2 BCKOFF1 BIT 7 6 5 4 3 2 1 0 R/W R R R R R/W R/W R/W R/W Reserved Reserved Reserved Reserved Enable Cadence timing on port 4 Enable Cadence timing on port 3 Enable Cadence timing on port 2 Enable Cadence timing on port 1 DESCRIPTION
Table 19. Timing Register
ADDRESS = 16h SYMBOL RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0] BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Restart timer programming bit 1 Restart timer programming bit 0 Startup timer programming bit 1 Startup timer programming bit 0 Overcurrent timer programming bit 1 Overcurrent timer programming bit 0 Load disconnect timer programming bit 1 Load disconnect timer programming bit 0 DESCRIPTION
Table 19a. Startup, Fault, and Load Disconnect Timers with Default Values in the Register 27h and 28h
BIT [1:0] 00 01 10 11 RSTR 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 x tFAULT tDISC tDISC nominal (350ms, typ) 1/4 x tDISC nominal 1/2 x tDISC nominal 2 x tDISC nominal tSTART tSTART nominal (60ms, typ) 1/2 x tSTART nominal 2 x tSTART nominal 4 x tSTART nominal tFAULT tFAULT nominal (60ms, typ) 1/2 x tFAULT nominal 2 x tFAULT nominal 4 x tFAULT nominal
ther extend the programming range of these timers and also increase the programming resolution. When the MAX5945 shuts down a port due to an extended overcurrent condition (either during startup or normal operation), if RSRT_EN is set high, then the part does not allow the port to power back on before the restart timer (Table 19a) returns to zero. This effectively sets a minimum duty cycle that protects the external MOSFET from overheating during prolonged output overcurrent conditions. A reset sets R16h = 00h.
Setting CL_DISC to 1 (Table 20) enables port-overclass current protection, where the MAX5945 scales down the overcurrent limit (VFLT_LIM) according to the port classification status. This feature provides protection to the system against PDs that violate their maximum class current allowance. A reset sets R17h = 0xC0. Power-enable pushbutton (Table 21) for SEMI and MANUAL modes. Setting PWR_ON_ to 1 turns on power to the corresponding port. Setting PWR_OFF_ to 1 turns off power to the port. PWR_ON_ is ignored
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 20. Miscellaneous Configurations
ADDRESS = 17h SYMBOL INT_EN RSTR_EN Reserved Reserved POFF_CL CL_DISC Reserved Reserved BIT 7 6 5 4 3 2 1 0 R/W R/W R R R R R/W R/W R/W A logic high enables INT functionality A logic high enables the autorestart protection time off (as set by the RSRT[1:0] bits) Reserved Reserved A logic high prevents power-up after a classification failure (I > 50mA, valid only in AUTO mode) A logic high enables reduced current-limit voltage threshold (VFLT_LIM) according to port classification result Reserved Reserved DESCRIPTION
Table 21. Power Enable Pushbuttons
ADDRESS = 19h SYMBOL PWR_OFF4 PWR_OFF3 PWR_OFF2 PWR_OFF1 PWR_ON4 PWR_ON3 PWR_ON2 PWR_ON1 BIT 7 6 5 4 3 2 1 0 R/W W W W W W W W W A logic high powers off port 4 A logic high powers off port 3 A logic high powers off port 2 A logic high powers off port 1 A logic high powers on port 4 A logic high powers on port 3 A logic high powers on port 2 A logic high powers on port 1 DESCRIPTION
Table 22. Global Pushbuttons
ADDRESS = 1Ah SYMBOL CLR_INT Reserved Reserved RESET_IC RESET_P4 RESET_P3 RESET_P2 RESET_P1 BIT 7 6 5 4 3 2 1 0 W W W W W R/W W A logic high clears all interrupts Reserved Reserved A logic high resets the MAX5945 A logic high softly resets port 4 A logic high softly resets port 3 A logic high softly resets port 2 A logic high softly resets port 1 DESCRIPTION
when the port is already powered and during shutdown. PWR_OFF_ is ignored when the port is already off and during shutdown. After execution, the bits reset to 0. During detection or classification, if PWR_ON_
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goes high, the MAX5945 gracefully terminates the current operation and turn-on power to the port. The MAX5945 ignores the PWR_ON_ in AUTO mode. A reset sets R19h = 00h.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 23. ID Register
ADDRESS = 1Bh SYMBOL BIT 7 6 ID_CODE 5 4 3 2 REV 1 0 R/W R R R R R R R R ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV [2] REV [1] REV [0] DESCRIPTION
ID register keeps track of the device ID number and revision. The MAX5945's ID_CODE[4:0] = 11000b. Contact the factory for REV[2:0] value.
Table 24. SMODE Register
ADDRESS = 1Ch SYMBOL Reserved Reserved Reserved Reserved SMODE4 SMODE3 SMODE2 SMODE1 BIT 7 6 5 4 3 2 1 0 CoR -- -- -- -- CoR CoR CoR CoR Reserved Reserved Reserved Reserved Hardware control flag for port 4 Hardware control flag for port 3 Hardware control flag for port 2 Hardware control flag for port 1 DESCRIPTION
Writing a 1 to CLR_INT (Table 22) clears all the event registers and the corresponding interrupt bits in register R00h. Writing a 1 to RESET_P_ turns off power to the corresponding port and resets only the status and event registers of that port. After execution, the bits reset to 0. Writing a 1 to RESET_IC causes a global software reset, after which the register map is set back to its reset state. A reset sets R1Ah = 00h. Enable SMODE function (Table 24) by setting EN_WHDOG (R1Fh[7]) to 1. SMODE_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. SMODE_ also goes high each and every time the software tries to power-on a port but is denied since the port is in hardware mode. A reset sets R1Ch = 00h. Set EN_WHDOG (R1Fh[7]) to 1 (Table 25) to enable the watchdog function. When activated, the watchdog timer counter, WDTIME[7:0], continuously decrements toward zero once every 164ms. Once the counter reaches zero
(also called watchdog expiry), the MAX5945 enters hardware-controlled mode and each port shifts to a mode set by the HWMODE_ bit in register R1Fh (Table 24). Use software to set WDTIME and continuously set this register to some non-zero value before the register reaches zero to prevent a watchdog expiry. In this way, the software gracefully manages the power to ports upon a system crash or switchover. While in hardware-controlled mode, the MAX5945 ignores all requests to turn the power on and the flag SMODE_ indicates that the hardware took control of the MAX5945 operation. In addition, the software is not allowed to change the mode of operation in hardwarecontrolled mode. A reset sets R1Eh = 00h. Setting EN_WHDOG (Table 26) high activates the watchdog counter. When the counter reaches zero, the port switches to the hardware-controlled mode determined by the corresponding HWMODE_ bit. A low in HWMODE_ switches the port into shutdown by setting
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 25. Watchdog Timer Register
ADDRESS = 1Eh SYMBOL BIT 7 6 5 WDTIME 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] DESCRIPTION
Table 26. Switch Mode Register
ADDRESS = 1Fh SYMBOL EN_WHDOG WD_INT_EN Reserved Reserved HWMODE4 HWMODE3 HWMODE2 HWMODE1 BIT 7 6 5 4 3 2 1 0 R/W R/W -- -- R/W R/W R/W R/W R/W Port 4 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires Port 3 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires Port 2 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires Port 1 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires Enables interrupt on SMODE_ bits DESCRIPTION A logic high enables the watchdog function
the bits in register R12h to 00. A high in HWMODE_ switches the port into auto mode by setting the bits in register R12h to 11. If WD_INT_EN is set, an interrupt is sent if any of the SMODE bits are set. A reset sets R1Fh = 00h. Use IGATE[2:0] (Table 27) to set the gate pin pullup current, IPU, according to the following formula: IPU = 50A - 6.25 x N where N is the decimal value of IGATE[2:0]. Use AC_TH[2:0] to program the current threshold of the AC disconnect comparator according to the following formula: IAC_TH = 213.68A + 28.33A x N where N is the decimal value of AC_TH[2:0]. Note: The programmed value has the same percentage tolerance as the value specified in the Electrical Characteristics. When set low, DET_BYP inhibits port power-on if the discovery detection was bypassed in AUTO mode.
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When set high, it allows the part to turn on power to a non-IEEE 802.3af load without doing detection. If OSCF_RS is set high, the OSC_FAIL bit is ignored. A reset sets R23h = 04h, which sets IPU = 50A and I AC_TH = 325A as shown in the Electrical Characteristics. Use R27h (Table 28) to program the current-limit threshold, VSU_LIM, and the nominal load disconnect detection time, tDISC nominal. Use IMAX[3:0] to program the current-limit trip voltage according to the following formula: VSU_LIM = 135mV + 19.25mV x N where N is the decimal value of IMAX[3:0]. The VFAULT_LIM limit scales proportionally to the VSU_LIM value (IFAULT = 88% of VSU_LIM). A reset sets R27h = 47h, which sets VSU_LIM = 212mV (typical) as shown in the Electrical Characteristics. The default threshold is set to meet the IEEE 802.3af standard when using an RSENSE = 0.5 1%, 100ppm.
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Quad Network Power Controller for Power-Over-LAN MAX5945
Table 27. Program Register 1
ADDRESS = 23h SYMBOL IGATE DET_BYP OSCF_RS AC_TH BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W IGATE[2] IGATE[1] IGATE[0] Detect bypass protection in AUTO mode OSC_FAIL Reset Bit AC_TH[2] AC_TH[1] AC_TH[0] DESCRIPTION
Table 28. Program Register 2
ADDRESS = 27h SYMBOL BIT 7 IMAX 6 5 4 3 TD_PR 2 1 0 R/W R R R R R R R R IMAX[3]. VSU_LIM programming bit 3. IMAX[2]. VSU_LIM programming bit 2. IMAX[1]. VSU_LIM programming bit 1. IMAX[0]. VSU_LIM programming bit 0. TD_PR[3]. tDISC nominal programming bit 3. TD_PR [2]. tDISC nominal programming bit 2. TD_PR [1]. tDISC nominal programming bit 1. TD_PR [0]. tDISC nominal programming bit 0. DESCRIPTION
Use TF_PR[3:0] to set the nominal value for t DISC according to the following formula: tDISC nominal = 238ms + 16ms x N where N is the decimal value of the binary words TF_PR[3:0]. A reset sets R27h = 47h, which sets tDISC nominal = 350ms as shown in the Electrical Characteristics. Use R27h in conjunction with the two TDISC[1:0] bits in register R16h to program the values of tDISC from 60ms to almost 340ms with a 16ms resolution.
Example: Set TD_PR[3:0] = 1111b, TDISC[1:0] = 11b Then: tDISC = 2 x tDISC nominal = 2 x (238ms + 16ms x 15) = 956ms Note: The programmed value has the same percentage tolerance as the value specified in the Electrical Characteristics.
______________________________________________________________________________________
33
Quad Network Power Controller for Power-Over-LAN MAX5945
Table 29. Program Register 3
ADDRESS = 28h SYMBOL BIT 7 TF_PR 6 5 4 3 TS_PR 2 1 0 R/W R R R R R R R R DESCRIPTION TF_PR[3]. tFAULT nominal programming bit 3. TF_PR[2]. tFAULT nominal programming bit 2. TF_PR[1]. tFAULT nominal programming bit 1. TF_PR[0]. tFAULT nominal programming bit 0. TS_PR[3]. tSTART nominal programming bit 3. TS_PR[2]. tSTART nominal programming bit 2. TS_PR[1]. tSTART nominal programming bit 1. TS_PR[0]. tSTART nominal programming bit 0.
Use the program registers (Table 29) to set the nominal value for tFAULT and tSTART for all ports according to the following formula: tFAULT nominal = 40.96ms + 2.72ms x N tSTART nominal = 40.96ms + 2.72ms x N where N is the decimal value of TF_PR[3:0] or TS_PR[3:0], respectively. A reset sets R28h = 77h, which sets tFAULT = tSTART = 60ms as shown in the Electrical Characteristics. Use R28h in conjunction with the two TSTART and TFAULT bits in register R16h to program the values of tFAULT and tSTART from about 20ms to almost 330ms with a 2.72ms resolution.
Example: Set TF_PR[3:0] = 1111b, TFAULT[1:0] = 11b Then: tFAULT = 4 x tFAULT nominal = 4 x (40.96ms + 2.72ms x 15) = 327ms Note: The programmed value has the same percentage tolerance as the value specified in the Electrical Characteristics.
34
______________________________________________________________________________________
Table 30. Register Map Summary
PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE
ADDR
REGISTER NAME
R/W
INTERRUPTS G G MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 AAA0,0A00 SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT 0000,0000
00h
Interrupt
RO
01h
Int Mask
R/W
EVENTS 4321 PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1 PWEN_ CHG4 PWEN_ CHG3 PWEN_ CHG2 PWEN_ CHG1 0000,0000 CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1 0000,0000
02h
Power Event
RO
03h 4321
Power Event CoR
CoR
04h
Detect Event
RO
05h 4321 LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2
Detect Event CoR
CoR
06h
Fault Event
RO
0000,0000 IMAX_FLT1
07h 4321 IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3
Fault Event CoR
CoR
08h
Tstart Event
RO
0000,0000 STRT_FLT2 STRT_FLT1
09h 4321 TSD VDD_OV VDD_UV VEE UVLO VEE_OV
Tstart Event CoR
CoR
0Ah
Supply Event
RO
0011,0101* VEE_UV OSC_FAIL VDD_UVLO
0Bh
Supply Event CoR
CoR
STATUS 1 reserved CLASS1[2] CLASS1[1] CLASS1[0] reserved DET_ST1 [2] reserved DET_ST2 [2] CLASS2[0] CLASS3[0] reserved DET_ST3 [2] CLASS4[0] PGOOD2 A3 PGOOD1 A2 reserved PWR_EN4 A1 DET_ST4 [2] CLASS4[1] PWR_EN3 A0 DET_ST1 [1] DET_ST2 [1] DET_ST3 [1] DET_ST4 [1] PWR_EN2 MIDSPAN DET_ST1 [0] DET_ST2 [0] DET_ST3 [0] DET_ST4 [0] PWR_EN1 AUTO 0000,0000
0Ch
Port 1 Status
RO
0Dh
Port 2 Status
RO
2
reserved
CLASS2[2]
CLASS2[1]
0000,0000
0Eh
Port 3 Status
RO
3
reserved
CLASS3[2]
CLASS3[1]
0000,0000
0Fh 4321 G reserved PGOOD4 PGOOD3 reserved
Port 4 Status
RO
4
reserved
CLASS4[2]
0000,0000 0000,0000 00A3A2, A1A0MA
10h
Power Status
RO
MAX5945
______________________________________________________________________________________
11h
Pin Status
RO
*UV and UVLO bits of VEE and VDD asserted depend on the order VEE and VDD supplies are brought up. A = AUTO pin state, A3..0 = ADDRESS pin states, M = MIDSPAN pin state, R = contact factory for current revision code Table 15a.
Quad Network Power Controller for Power-Over-LAN
35
MAX5945
Quad Network Power Controller for Power-Over-LAN
36
PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE 4321 P4_M1 P4_M0 P3_M1 P3_M0 P2_M1 P2_M0 P1_M1 P1_M0 AAAA,AAAA 4321 ACD_EN4 ACD_EN3 ACD_EN2 ACD_EN1 DCD_EN4 DCD_EN3 DCD_EN2 DCD_EN1 0000,AAAA 4321 4321 G G INT_EN RSTR_EN reserved reserved POFF_CL CL_DISC reserved RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] reserved reserved reserved reserved Bckoff4 Bckoff3 Bckoff2 Bckoff1 TDISC[0] reserved CLASS_EN4 CLASS_EN 3 DET_EN4 DET_EN3 DET_EN2 DET_EN1 CLASS_EN CLASS_EN 2 1 AAAA,AAAA 0000,MMMM 0000,0000 1100,0000 G 4321 G CLR_INT reserved reserved RESET_IC RESET_P4 RESET_P3 PWR_OFF4 PWR_OFF3 PWR_OFF2 PWR_OFF1 PWR_ON4 PWR_ON3 reserved reserved reserved reserved reserved reserved reserved PWR_ON2 RESET_P2 reserved PWR_ON1 RESET_P1 0000,0000 0000,0000 G 4321 G G 4321 EN_WHDOG WD_INT_EN reserved reserved WDTIME[7] WDTIME[6] reserved reserved reserved reserved reserved reserved reserved reserved SMODE4 Reserved ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV [2] SMODE3 reserved REV [1] SMODE2 reserved REV [0] SMODE1 reserved 1100,0RRR 00000000 00000000 00000000 HWMODE4 HWMODE3 HWMODE2 HWMODE1 00000000 WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] G G G 4321 G G G G G TF_PR[3] IMAX[3] reserved reserved IMAX[2] TF_PR[2] reserved reserved reserved reserved IGATE[2] IGATE[1] reserved reserved reserved IGATE[0] reserved reserved reserved IMAX[1] TF_PR[1] reserved reserved reserved reserved reserved reserved reserved reserved reserved DET_BYP reserved reserved reserved IMAX[0] TF_PR[0] Reserved Reserved Reserved OSCF_RS Reserved Reserved Reserved TD[3] TS_PR[3] reserved reserved reserved AC_TH[0] reserved reserved reserved TD[2] TS_PR[2] reserved reserved reserved AC_TH[0] reserved reserved reserved TD[1] TS_PR[1] reserved reserved reserved AC_TH[0] reserved reserved reserved TD[0] TS_PR[0] 00000000 00000000 00000000 00000100 00000000 00000000 00000000 01000111 01110111
Table 30. Register Map Summary (continued)
ADDR
REGISTER NAME
R/W
CONFIGURATION
12h
Operating Mode
R/W
13h
Disconnect Enable
R/W
14h
Det/Class Enable
R/W
15h
Backoff Enable
R/W
16h
Timing Config
R/W
17h
Misc Config
R/W
PUSHBUTTONS
18h
Reserved
R/W
19h
Power Enable
WO
1Ah
Global
WO
GENERAL
1Bh
ID
RO
1Ch
SMODE
CoR
1Dh
Reserved
1EH
Watchdog
R/W
1FH
Switch Mode
R/W
MAXIM RESERVED
20H
Reserved
21H
Reserved
22H
Reserved
23H
Program1
R/W
______________________________________________________________________________________
24h
Reserved
25h
Reserved
26h
Reserved
27H
Program2
R/W
28H
Program3
R/W
*UV and UVLO bits of VEE and VDD asserted depend on the order VEE and VDD supplies are brought up. A = AUTO pin state, A3..0 = ADDRESS pin states, M = MIDSPAN pin state, R = contact factory for current revision code Table 15a.
Quad Network Power Controller for Power-Over-LAN MAX5945
Applications Information
PSE (SWITCHES/ROUTERS, ETC)
PD (IP PHONE, WIRELESS ACCESS POINT, SECURITY CAMERAS, ETC.)
DATA PHY
RJ-45
RJ-45
DATA PHY LOAD
POWER
POWER AND DATA OVER TWISTED-PAIR ETHERNET CABLE
POWER
MAX5020
GND -48V -48V TO +3.3V DC-DC
3.3V
MAX5945
QUAD PoE CONTROLLER
MAX5940B
PD INTERFACE CONTROLLER
-48V
MAX5014
DC-DC CONVERTER VOUT
OR
MAX5941/MAX5942
PD INTERFACE AND DC-DC CONVERTER
Figure 14. PoE System Block Diagram
______________________________________________________________________________________
37
Quad Network Power Controller for Power-Over-LAN MAX5945
RJ-45 CONNECTOR 1 3 PHY RD1+ RD1RX1+ RX124 22 1 2 3 6 -48VOUT 0.1F RXT1 23 75 1000pF 250VAC 75 75 75 0.1F 4 5 0.1F TXCT1 20 0.1F 7 8
1/2 OF 21 H2005A TX1+ 4 TD1+ 19 TX15 TD1-
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V, (REF TO DGND) 3k 180 VDD VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5945
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT
1k
1N4448
-48V FDT3612 100V, 120m SOT-223 1N4002
1 OF 4 CHANNELS
Figure 15. PoE System Diagram of One Complete Port, Endpoint PSE
38
______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN MAX5945
RJ-45 CONNECTOR 1 2 DATA 3 6
4 5 7 -48VOUT 8
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V (REF TO DGND) 3k 180 VDD VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5945
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT
1k
1N4448
-48V FDT3612 100V, 120m SOT-223 1N4002
1 OF 4 CHANNELS
Figure 16. PoE System Diagram of One Complete Port, Midspan PSE
______________________________________________________________________________________
39
Quad Network Power Controller for Power-Over-LAN MAX5945
R10 2 R6 1 C3 15nF R5 1k Q4 MMBTA56 DRAIN 1 2 C6 0.47F 100V 3 4 V+ VDD FB SS_SHDN C4 220F Sanyo 6SPS220M L1 68H, DO3308P-683 D1 DIODES INC.: B1100 R1 2.6k
+3.3V
+3.3V
300mA C5 4.7F
GND GND
Q2 MMBTA56 GND
MAX5020
VCC NDRV GND CS
8 7 6 5
R8 30
GATE SOURCE
Q1 Si2328 DS C9 4.7H C7 0.22F
Q3 MMBTA56
C2 0.022F -48V -48V
C1 0.1F
C8 2.2F
R4 1
R9 1
R2 6.81k R7 1.02k
R3 2.61k
Figure 17. -48V to +3.3V (300mA) Boost Converter Solution for VDIG
1700 (mils)
1700 (mils)
1700 (mils)
965 (mils)
965 (mils)
Figure 18. Layout Example for Boost Converter Solution for VDIG
40
______________________________________________________________________________________
965 (mils)
Quad Network Power Controller for Power-Over-LAN
Component List
DESIGNATION C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 Q1 Q2 Q3 Q4 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 U1 DESCRIPTION 0.1F, 25V ceramic capacitor 0.022F, 25V ceramic capacitor 15nF, 25V ceramic capacitor 220F capacitor Sanyo 6SVPA220MAA 4.7F, 16V ceramic capacitor 0.1F, 100V ceramic capacitor 0.22F, 16V ceramic capacitor 0.22F, 16V ceramic capacitor 4.7nF, 16V ceramic capacitor B1100 100V Schottky diode 68H inductor Coilcraft DO3308P-683 or equivalent Si2328DS Vishay n-channel MOSFET, SOT23 MMBTA56 small-signal PNP MMBTA56 small-signal PNP MMBTA56 small-signal PNP 2.61k 1% resistor 6.81k 1% resistor 2.61k 1% resistor 1 1% resistor 1k 1% resistor 1 1% resistor 1.02k 1% resistor 30 1% resistor 1 1% resistor 2 1% resistor High-voltage PWM IC MAX5020ESA (8-pin SO)
Chip Information
TRANSISTOR COUNT: 148,768 PROCESS: BiCMOS
MAX5945
______________________________________________________________________________________
41
Quad Network Power Controller for Power-Over-LAN MAX5945
Typical Operating Circuits
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD -48V RTN OUTPUT TO PORT VDD
AGND
A0
A1
A2
A3
1k
3k VCCRTN SDAOUT OPTIONAL BUFFER 3k
RESET INTERNAL 50k PULLUP INT AUTO SDAIN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) N.C. 4.7k
SERIAL INTERFACE
HPCL063L 180
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5945
MIDSPAN OSC_IN
3k SCL HPCL063L
SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1N4448 -48V OUTPUT TO PORT
1k
-48V FDT3612 100V, 120m SOT-223 NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN VEE AND (AGND + 4V). 1 OF 4 CHANNELS CAN BE UP TO 100k
Typical Operating Circuit 1 (without AC Load Removal Detection)
42
______________________________________________________________________________________
Quad Network Power Controller for Power-Over-LAN
Typical Operating Circuits (continued)
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD -48V RTN OUTPUT TO PORT
MAX5945
VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5945
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V -48V OUTPUT TO PORT
1k
1N4448
-48V FDT3612 100V, 120m SOT-223 NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND MUST BE CONNECTED DIRECTLY TO AGND FOR AC DISCONNECT DETECTION CIRCUIT TO OPERATE. 1 OF 4 CHANNELS 1N4002
CAN BE UP TO 100k
Typical Operating Circuit 2 (with AC Load Removal Detection)
______________________________________________________________________________________
43
Quad Network Power Controller for Power-Over-LAN MAX5945
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
36
INCHES DIM A A1 B C e E H L D MAX MIN 0.096 0.104 0.004 0.011 0.012 0.017 0.013 0.009 0.0315 BSC 0.299 0.291 0.398 0.414 0.040 0.020 0.598 0.612
MILLIMETERS MAX MIN 2.65 2.44 0.29 0.10 0.44 0.30 0.23 0.32 0.80 BSC 7.40 7.60 10.11 10.51 0.51 15.20 1.02 15.55
E
H
1
TOP VIEW
D A1 e A C 0-8
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL DOCUMENT CONTROL NO. REV.
21-0040
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SSOP.EPS


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